The combination of conduction currents and high fields in a MOSFET will lead to impact ionization, causing a non-ideality presenting as a monotonically increasing drain current with drain voltage. It may result in a device malfunction when the device operates in high gate and drain bias condition, for example, see Cornell, M. E., Williams, R. K., and Yilmaz, H., “Impact Ionization in Saturated High-Voltage LDD Lateral DMOS FETs”, Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs, pp. 164-167, April 1991. This impact ionization would cause an avalanche breakdown of the power switch in a power management apparatus such as boost circuit, buck circuit and inverter circuit, when the power switch is turning on fast to maintain high efficiency. In further detail, referring to FIG. 1, a boost circuit 100 comprises a PWM controller and logic 102 for producing a control signal, a drive circuit 104 connected to the PWM controller and logic 102 for producing a drive signal according to the control signal, and a power output stage 101 connected between a power input VIN and ground GND for converting the input voltage VIN to an output voltage VOUT according to the drive signal provided by the drive circuit 104. The drive circuit 104 includes a driver 106 connected to the PWM controller and logic 102 and a buffer unit 109 connected between the driver 106 and the power output stage 101. The buffer unit 109 includes inverter gates 108 and 110 coupled in series and connected with an operation voltage PVDD. The power output stage 101 includes a power switch 112 connected between a phase node 114 and ground GND, and is alternatively turned on and off by the drive signal, an inductor 116 connected between the power input VIN and the phase node 114 to store and release energy by turning on and off the power switch 112, and a rectifier diode 118 connected between the phase node 114 and the power output VOUT for maintaining a current I flowing from the phase node 114 to the power output VOUT. FIG. 2 shows an implementation of the power switch 112, in which a plurality of NMOS transistors 120-124 are parallel connected together in such a manner that all the drains are connected to the phase node 114, all the sources are connected to ground GND, and all the gates are connected together. However, although such configuration can be regarded as an equivalent NMOS switch for the power switch 112, there are always parasitic resistors 126-128 each between two adjacent gates and parasitic capacitors 130-132 each between a gate and ground GND in the chip. The parasitic resistors 126-128 and capacitors 130-132 may result in non-uniform turn on of the NMOS 120-124. FIG. 3 shows the I-V curves of the power switch 112 when it is driven. Referring to FIGS. 2 and 3, when the power switch 112 is fast turning on, the first NMOS transistor 120 will be turned on first, and the other NMOS transistors 122-124 will not be turned on at the same time due to the RC delays, resulting in the real I-V curve 138 deviated from the ideal I-V curve 136, and thereby the earlier turned on NMOS transistor 120 operating in a high gate and drain bias region 134. This high gate and drain bias condition will easily result in impact ionization in the turned on NMOS 120, and further cause an avalanche breakdown thereof and thereby device failure. To improve thereto, conventionally, the power switch 112 is slowly turned on or the manufacturing process of the power switch 112 is improved, in order to eliminate the non-uniform turning on of the power switch 112. However, slow turn on of the power switch 112 will increase the state transition time of the power management apparatus 100, thereby causing efficiency degradation, and improved manufacturing process of the power switch 112 could merely reduce the parasitic resistors 126-128 and the parasitic capacitors 130-132, but couldn't eliminate them completely, even with considerable cost and time.
Therefore, it is desired a high efficiency and low cost power management apparatus having an extended safe operation region and an operation method thereof.